Write-Time Compensation for 2,7 Code
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18
The 2,7 run-length-limited code requires an increasingly complex write-time compensation scheme as the linear bit density increases. The circuit shown above delays a given transition to correct for the inherent asymmetry of an isolated readback pulse. Even if the time periods between the given transition and its closest preceding and following transitions are equal (provided these time periods are relatively short), the circuit corrects for asymmetry. The logic diagram of Fig. 1 contains an eleven-bit shift register which holds in its middle latch the transition to be compensated. The register also holds any preceding or following transitions which may cause the transition residing in the middle of the register to be detected late or early due to "bit shift".