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Local Storage Organization With Simultaneous Read and Write Disclosure Number: IPCOM000063970D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

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Wassel, ER [+details]


Processor data flow organization (Fig. 2) can lower array requirements for a local storage application and improve data flow performance. Access to an array is typically performed over a single address path for both read and write operations. For the local storage (i.e., Register Storage) function in a processor with an overlapped data destination operation (Fig. 1a), it is necessary to access the local store twice per cycle. This type of operation is shown by the timing diagram in Fig. 1b. Note that because of the timing sequence, it is necessary to provide the D register to the A/B register path. This path allows operations which update, then use, a given register in two successive cycles, in that order.