Branch Path Prediction Using Associative Register Pairs
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18
A given branch instruction, located within a program, has a high probability of always branching or never branching each time it is executed. Where the tendency is to branch, it is probable that it will be to the same target instruction address as the last time it was executed. This information is used to implement more sophisticated instruction buffer (I-buffer) algorithms for higher performance processors. Such implementations include Decision History Tables (DHTs) and Branch History Tables (BHTs) with either (or both) target instruction storage address or target instruction location within the I-buffer. A set of register pairs 2,3 can be utilized for successful branches.