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Integrating Time Domain Filter Disclosure Number: IPCOM000063982D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

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Buhler, OR Emeigh, RD [+details]


This integrating time domain filter is a signal processing scheme amenable to peak-detecting read channels. In operation, this system eliminates the detection of erroneous zero crossings by requiring that valid zero crossings be separated by a minimum time period. A differentiated signal 23, whose zero crossings represent the peaks of the undifferentiated signal, drives a comparator with differential outputs Q on line 10 and Q on line 11. Multiplexer 12 steers the proper comparator output to integrator 13. From the timing diagram it can be seen that initially multiplexer 12 routes comparator output 10 to integrator 13. Integrator output 24 ramps up until it is equal in value to reference 15. When this occurs, comparator 14 produces an output signal 18 that sets S/R flip-flop 19 which then produces output signal Dpulse 20.