Late Address Concept for Semiconductor Memories
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18
Proposed is a late address concept of the type previously described [*], which offers shorter delay and return-to-zero times, lower power requirements and improved extendability to a higher number of buffers without a significant loss of performance. The improved circuit is shown in the drawing; for details, attention is drawn to [*]. During standby or writing, the data-out gate (DOG) inputs DG0 to DG3 are at up level, so that the data-out transistor TD0 is turned off. During reading, information is read from the cells (not shown) and entered into the buffer. At that stage, one DOG signal becomes active (late address), selecting one out of 2, 4 or more buffers and simultaneously enabling the output driver. No glitch can occur at the output.