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Buffered Logic/Cvs ROS

IP.com Disclosure Number: IPCOM000063998D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Erdelyi, CK [+details]

Abstract

This article describes a method which applies buffered logic or cascode voltage switch (CVS) technology to design a read-only storage (ROS). This method is preferrable to the conventional array design because it can utilize the same design tools as the random logic design. In addition, it results in better performance and functional density. Fig. 1 shows a ROS utilizing buffered logic or CVS trees. Fig. 2 shows a ROS utilizing buffered logic/CVS trees capitalizing on N common terms which results in less complex trees. Fig. 3 shows an extension of the design to large address space. Both approaches are aimed at reducing the tree complexity. The multiplexers may be implemented by using M additional trees.