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CMOS Delay Circuit Disclosure Number: IPCOM000064006D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

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Haug, W Helwig, K Loehlein, WD Mueller, R [+details]


A delay circuit comprising only two CMOS inverters is described that is able to generate different delays for the rising and the falling pulse slopes (asymmetrical delays) and that can influence the gradients of the output pulse. Instead of using a chain of multiple inverter stages, only two CMOS inverter stages are serially connected which are sufficient for generating pulse delays with all kinds of pulse shapes. The first inverter stage comprises a P and an N channel FET T1 and T2 which are serially connected to a supply voltage VH . This first inverter stage is used to adjust the delays dr, df of an incoming slope at input VIN to the slope at output VOUT, whereas the second inverter stage, comprising P and N channel FETs T3, T4, is used to define the gradients of the output slope.