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Timing Chain With Relocatable Phases and Multiple Performers

IP.com Disclosure Number: IPCOM000064015D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Gray, KS [+details]

Abstract

Field-effect transistor (FET) dynamic random-access memories (DRAMs) are one of two main types based on speed/density. The chip is either fast and less dense having fewer phases or slow and more dense having additional phases. A method is described in which programmable timing chains are used to alter the overall performance of the chip by reducing the effective number, and associated function, of certain timing phases. Normally a delay stage input comes from the output of the previous delay stage. A programming pad or an on-chip fuse output (CP), a CP inverter and a steering circuit are used to allow a delay stage input to come from one of two different places. The CP inverter (Fig. 1) takes a programming pad or fuse voltage and generates the complement voltage (VH or Gnd). The steering circuit (Fig.