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Distributed Bias Circuit for Masterslice Applications Disclosure Number: IPCOM000064021D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue


Related People

Askin, HO Smith, GE [+details]


A distributed bias network for masterslice logic gates is shown in Fig. 1. Part 1 of Fig. 1 (shown in Fig. 2) forms a reference supply for part 2 of Fig. 1 (shown in Fig. 3). There is one part 1 circuit per chip. The output of part 1 drives 200 part 2 circuits which are distributed over the same chip. Part 2 is an emitter follower local bias supply circuit which drives individual logic circuits. The part 2 circuits can be placed on the chip as needed in a given design. They can be made from gate parts using single devices of sufficient size or using the parallel devices shown in the diagram. By operating logic circuits on a locally generated bias supply, variations in supply voltage due to regulator tolerances and line drops tend to be minimized.