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Self-Aligned Polysilicon Bipolar Transistor Emitter-Base Window

IP.com Disclosure Number: IPCOM000064027D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Desilets, KR Dockerty, RC Schepis, DJ Wheeler, DC [+details]

Abstract

Opening the emitter in the self-aligned dSi base transistor presents the following problems in the manufacture of integrated circuit bipolar transistors. One must choose a mask-etch technique which provides reproducibly (1) a vertical profile suitable for subsequent sidewall formation (2) an end-point detection scheme to etch dSi over Si stopping on Si, (3) a clean specular Si surface after removal of dSi, (4) line width control and, finally, (5) process simplicity. The process employs multilayered resist, SiO2 and/or Si3N4 masks with BHF and CF4 reactive ion-etching (RIE). End-point detection is accomplished via dSi over a dielectric in a fiducial. The particular CF4 RIE process employed etches Si, SiO2, etc., with low selectivity; i.e., these films are subtracted at approximately the same rate.