MOSFET Clock Driver Circuit With Delay- and Power-Saving Features
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18
This self-isolating MOSFET bootstrapped clock driver circuit minimizes power dissipation during the time when the clock driver is neither charging nor discharging its particular phase line. The circuit also provides a minimum output delay from the input phase. By isolating the gates of the output driver devices from the bootstrap capacitor during the delay time required for precharge, the DC current path normally created through the driver and pull-down devices is eliminated. This permits the output capacitor to be charged efficiently in the minimum amount of time. In the figure, clock phase 1 is a reset signal preceding phase 3. As phase 1 goes high, devices 15 and 21 turn on, pulling node 7 to ground and allowing node 6 to rise to one depletion threshold below phase 1 (+5 V).