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One-Dimensional Transistor Arrays for Logic Circuits With Fixed Incidence Structure

IP.com Disclosure Number: IPCOM000064030D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Chen, CL Johnson, EL Otten, RH [+details]

Abstract

CMOS single-ended cascode-voltage-switch (SCVS) or domino-CVS can be used for building high performance, low power logic circuits on a VLSI chip. This article describes a layout technique for implementing domino-CVS circuits generated by a logic synthesis technique. This layout technique transforms the logic diagram, obtained by translating a boolean expression directly into a two-terminal series-parallel graph, into a one-dimensional transistor array on a single diffusion strip with the minimum number of transistors. The set of logic signals connected to the gates of the transistors having one of the other contacts at the same voltage is not changed by the algorithm. This is important when a particular graph topology has been chosen to prevent charge-sharing problems. The logic function given in Fig.