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Clock Driver for Polarity Hold Latch

IP.com Disclosure Number: IPCOM000064038D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Lohrey, FH Mullgrav, AL [+details]

Abstract

The clock driver circuit of Fig. 1. generates complementary clock control signals for polarity-hold latches. Logic block representation and timing relationships are shown in Fig. 2. The two main features of this circuit are: 1. It guarantees that the latch operation will be hazard-free (no chance of incorrect data being stored). This is accomplished by the built-in one block delay "D 4", as shown in Fig. 2. 2. It guarantees that the latch operation will be glitchless (no momentary outputs when latch is opened). This is accomplished by the built-in one block delay "D 2", as shown in Fig. 2.