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Chip-Redundant Wiring Technique

IP.com Disclosure Number: IPCOM000064073D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Curtin, JJ Dorler, JA Mikhail, WF Mooney, DB [+details]

Abstract

Redundant circuits (books or elements) and redundant wires may be employed on semiconductor chips. This article describes a simple method for enabling auto-wiring programs to select the most advantageous wiring paths to wire the redundant elements. The chip is assumed to contain four wiring planes with the following layout: Plane 1----vertical wires Plane 2----horizontal wires (plane pair 1 and 2) Plane 3----vertical wires Plane 4----horizontal wires (plane pair 3 and 4) In Fig. 1, redundant circuits, books, or elements are laid out with vertical adjacency, and the wiring plane selection can be determined by simply identifying the direction (up or down) that the wire is going to or from each of the Logic Service Terminals (LSTs). Since the LSTs are also redundant, they are also swappable (A and A', B and B', etc.).