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Single-Device DRAM Cell Using Butted Plate Disclosure Number: IPCOM000064098D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

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Chao, HH Iyer, SS Ning, TH [+details]


This article relates generally to integrated circuit fabrication and more particularly to the construction of a capacitor for a storage cell. The storage capacitor for a dynamic random-access memory (DRAM) cell can be constructed without overlap of the capacitor plate and gate or contamination of the capacitor. Referring to Fig. 1, the active area 1 of wafer 2 is delineated using known techniques. Gate oxide 3 is grown, and a layer 4 of heavily doped n-type polysilicon is deposited. Polysilicon layer 4 is capped with silicon dioxide layer 5 and a second heavily doped n type polysilicon layer 6. This stack is then patterned, and silicon dioxide sidewall spacers 7 are added using chemical vapor deposition and reactive ion etching of silicon dioxide. In Fig.