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MFM/FM Encoder Using Special D-Flip-Flops

IP.com Disclosure Number: IPCOM000064111D
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Henning, LR Hoffman, RD Nicholson, JO Tiberino, EJ [+details]

Abstract

A special edge-triggered D-flip-flop 10 is shown in detail in Fig. 1 and schematically in Fig. 2. D-flip-flop 10 is built from primitives, six NAND gates. This allows access to all of the internal signals in the flip-flop. Fig. 1 also establishes some signal naming conventions for the following discussion. Figs. 3A and 3B are the logic state transition diagrams for the D-flip-flop pictured in Fig. 1. Fig. 3 tabulates the results of appropriate Next State Equations: Y1 = (CLK) y1 + Dy2 _____ _________ Y2 = y1 + (CLK) + Dy2 Z1 = (CLK)(y1) Fig. 3 shows the six stable states for the y1y2 state machine and shows to which stable states the unstable states will switch. It is important to note in this analysis that Z1 is stable during +CLK=1.