Browse Prior Art Database

Improved FET Structure Using Silicide Junctions

IP.com Disclosure Number: IPCOM000064113D
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
El-Kareh, BT Noble, WP [+details]

Abstract

Field-effect transistors (FETs) may be formed by the deposition of a conductor level which acts as a source of dopant for the source and drain pockets. The gate is then deposited as a second level of conductor, deposited after the source and drain pockets are defined. Since the channel length of such a device is determined by the minimum definable space between conducting lines and the lateral impurity diffusion, the minimum obtainable channel length is limited. This article teaches that a reduction in channel length and junction grading can be obtained by depositing a doped oxide and directionally etching it such as to form insulating spacers on the source and drain conductor sidewalls.