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Dual-Mode Error Correction and Error Detection Disclosure Number: IPCOM000064123D
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18

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Chen, CL [+details]


An error correction and error detection scheme for a (40,32) code is described. The code is an SEC-DED code when it is used in a by 1 chip organization, and the code is a single chip error correcting code (ECC) when it is used in a by 4 chip organization. The code can be implemented with the same logic circuitry for both modes of chip organizations. Fig. 1 shows the parity check matrix of the (40,32) code. The matrix is used to generate 8 ECC check bits for a block of 32 data bits. The vertical lines indicate the 4-bit package boundaries for the by 4 mode. Fig. 2 shows the block diagram of the error correction and error detection for the code. The first 4 bits and the last 4 bits of the syndrome are designated as S1 and S2, respectively, i.e., S1=(s1, s2, s3, s4) and S2=(s5, s6, s7, s8). Let E1 (I), I=1,2,...