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Modified Ones Complement Carry-Completion-Sensing Adder

IP.com Disclosure Number: IPCOM000064128D
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Aggarwal, BK Sinha, B [+details]

Abstract

A technique is described whereby a circuit modification is made to the ones complement carry-completion-sensing adder [*], so as to also perform an A + A operation, where A is an n-bit binary number. In the referenced ones complement carry-completion-sensing adder, the completion of the operation, indication DONE signal, is never generated if the two numbers are A and A . The referenced circuit, as shown in Fig. 1, of a ones complement carry-complement-sensing adder, and Fig. 2, of the referenced interior logic of the carry-propagation (CP) cell 10, will never generate a DONE signal 11 should a condition exist where B-input (Bi) 12 is equal to the A--input (A-i) 13, to indicate the completion of the addition process. Modified versions of this circuit, as shown in Figs.