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Common Conductor Layout for Printed Circuit Board With Mixed Grids

IP.com Disclosure Number: IPCOM000064140D
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Baldauf, LM Girvan, EJ Graf, TS Morgan, RC [+details]

Abstract

The figure illustrates a conductor layout for a printed circuit (PC) board which is adapted to receive components that are located relative to two different grid patterns . In the layout as shown, the wiring tracks 10 are defined first. The via holes 11 and 12 are then placed where they are required and are dealt with as blockages as the layout of the board proceeds. If the 2 grid patterns of the holes are modular, then the tracks 10 are common to both grids . With such a scheme wire routing around a through hole or a hole for receiving a pin or lead is a simple matter of changing tracks. These changes are made at the intersection of horizontal and vertical tracks 13 and 10.