Fully Microcode-Controlled Emulation Architecture
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18
This article describes the hardware and microcode implementation for a relatively non-complex emulator to convert a macro instruction to one or more micro instructions, which micro instructions run on an instruction processing unit. A simplified system configuration consists of an instruction processing unit (IPU) 11, an instruction storage unit (ISU) 12, a data storage unit (DSU) 13 and the emulator bus unit (EBU) 14. ISU 12 and DSU 13 may take the form of separate caches, a single cache or a single low speed storage unit. EBU 14 attaches to the instruction bus 15 and to the buses making up the internal bus, an address/data-out bus 16, data-in/out bus 17 and a control bus 18. EBU 14 also communicates with a dedicated read-only storage (ROS) 19 for a subset of its control instructions.