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Process for Sub-Micron Circuit Fabrication

IP.com Disclosure Number: IPCOM000064265D
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Brady, MJ Davidson, A Faris, SM Malozemoff, AP [+details]

Abstract

This article relates generally to the fabrication of integrated circuits and more particularly to the use of "hole and cave" to enable deposition by shadowing to accurately define sub-micron circuit areas. The use of a "hole and cave" in combination with variable angle shadowing of deposition beams permits accurate control of the adjacent deposition areas without requiring the same location accuracy of the beam sources. An enlarged cave can be made to accommodate multiple circuit devices through one or more holes in a stencil, and contact areas can be larger than the hole size. An example of circuit fabrication using "hole and cave" is shown in the figures. Referring to Fig. 1, two layers of different metals 1 and 2 are deposited onto a p-type silicon wafer 3 and metal layer 1 is coated with photoresist 4, indicated in phantom.