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Wiring Aid for Depopulated VLSI Logic Chips Disclosure Number: IPCOM000064266D
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18

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Diepenbrock, JC Hsi, CC Mikhail, WF [+details]


Modern VLSI (very large-scale integration) chip designs employ a "depopulation" technique to enable wiring variable numbers of circuits on logic chip designs where varying complexity of function requires different amounts of wiring space per used circuit. This technique involves designing more logic cells into a gate array chip than required to implement the desired average function, with the unused cells providing wiring space for interconnections between circuits. As the size of gate array chips has increased, however, difficulty is often experienced in wiring a given system function due to those relatively small parts of such functions that contain highly interconnected, complex logic.