Browse Prior Art Database

New Scheme to Form Shallow N+ and P+ Junctions for Mos Devices

IP.com Disclosure Number: IPCOM000064273D
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Chao, HH Taur, Y Ting, CY Wang, LK [+details]

Abstract

This article relates generally to methods for fabricating integrated circuits and more particularly to methods for forming very shallow n+ and p+ junctions for submicron CMOS technology. Still more particularly it relates to methods of forming shallow junctions using ion- implanted silicide and polycrystalline regions which are out-diffused to form shallow junctions. Fig. 1 shows a cross-sectional view of a complementary metal-oxide-semiconductor device (CMOS) after polysilicon gates 2 having oxide sidewalls 3 have been fabricated on semiconductor substrate 4. A silicide-forming metal is then deposited on recessed oxide (ROX) regions 5, gates 2, sidewalls 3 and the exposed surface of substrate 4. Substrate 4 is then annealed forming self-aligned, silicide regions 6. Fig.