Organizational Redundancy for a Parallel Processor Machine
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18
A machine organization for switch-network-connected parallel processor-type machines is provided that incorporates incremental redundancy logically consistent with the existing machine organization by adding a spare processor cluster to the existing n clusters and modifying the connected switch node design to involve 2n+2 (n+1)x(n+1) switch nodes. In addition, each multiplexer or each processor has a logical-to-physical processor address ID mapping function that is applied to all outgoing traffic, and a global control function is used to preside over all the processor clusters for bring up and diagnosis and to exercise control over sparing and processor address ID mapping updates.