Row Address Buffer and Decoder Circuits for CMOS Dynamic Ram
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18
In this publication, a new set of row address buffer and decoder circuits is introduced for CMOS DRAM, which has lower noise and power as well as higher noise margin and speed than conventional dynamic or static address buffer and decoder designs. The result is important because of the quadrupling of the number of decoders and larger capacitance loading of each new generation of DRAM. The address buffer is used to latch the signal on address bus into the chip to drive the decoders. The decoder generates the 2n outputs from n binary input variables and gives one and only one output line having distinguished state from the remaining (2n-1) ones. The conventional DRAM design uses NMOS technology. In order to save power and to gain speed, dynamic NMOS circuits are used.