Browse Prior Art Database

Three-State RAM Design Scheme

IP.com Disclosure Number: IPCOM000064312D
Original Publication Date: 1985-Jun-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Wu, PT [+details]

Abstract

This technique provides a means to store/read three levels in a single RAM (random-access memory) cell using conventional binary RAM circuitry. With three states, two RAM storage cells provide 3 binary bits--effectively increasing storage density 1.5X without increasing the RAM storage area. It is apparent that the low-cost, dynamic RAM offerings of today also offer relatively high performance. But, there are some systems that do not need such high performance and would exchange performance for lower cost. This technique features a three-state RAM design that lowers RAM performance 2.5X but increases storage density 1.5X. The RAM operates in a +5, 8.5-volt environment that stores three levels (0, 4, and 8 volts). The RAM cell size is equivalent to the cell size in a +5-volt environment.