Parallel Pipeline Multiplier in a Signal Processor
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-18
A parallel pipeline multiplier with enhanced performance and flexibility including extended precision operation and scaling control on input and output variables is described. Control is provided which permits the contents of the multiplier to be saved and restored when the processor is interrupted. Partial product and complete product registers operate simultaneously during each clock cycle. In the event of interrupt, the contents of both registers are saved and restored. This is a critical requirement for multipliers which employ pipeline operation to achieve throughput performance. The parallel pipeline multiplier is an integral part of the arithmetic flow of a signal processor. The following are significant attributes of the multiplier which may be unique and of general application. 1.