High Speed Bus Arbiter for Bus-Oriented Multiprocessor Systems
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-18
An arbitration unit is described for a typical multiprocessor system consisting of several minicomputers or advanced microcomputers connected to a single bus and a common or shared memory resource. In such a system, bus traffic can be the limiting factor on system throughput. Because of this, it is necessary that the arbitration between multiple requests be resolved in a short period of time. The described arbitration unit is a high speed, decentralized, asynchronous unit that employs a "round-robin" dynamic priority algorithm. A typical time-shared/common bus 8 multiprocessing system is illustrated in Fig. 1.. A system memory comprises a centralized memory 10 and distributed memories 12 and 14 which are respectively distributed to processors 16 and 18.