Error Tracing Arrangement of a Pipelined Processor
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-18
Error tracing in a pipelined machine is complicated by the fact that an error is not generally detected in the same machine clock phase in which it occurs. Thus some analysis is necessary to discover just which instruction or data storage address is associated with an error. In this signal processor, error analysis is facilitated by using the instruction link register (ILR) in the processor as a pointer when an error occurs. To do this, the ILR is locked when an error is detected so its contents can be used in the error analysis routine. This disclosure relates to an alternative way of saving pointers for error analysis that is simpler to use, provides more extensive error analysis, and eliminates the need for NOP insertion (for certain branch sequences) when error detection is enabled.