Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-18
This article describes an anti-hangup circuitry and method which eliminates the hangup problem in a burst modem clock recovery phase-locked loop (PLL). Such a phase-locked loop has a relatively slow phase acquisition characteristic when the initial phase error is near the null point of the phase detector transfer characteristics (that is, Å180Œ). In this case, the PLL takes a much longer time to lock because of a small correction voltage generated from the phase detector. The technique, therefore, is to monitor the initial phase error, and when it falls outside of a predetermined range, a circuit generates an error voltage signal whose magnitude is greater than the magnitude of the normal phase detector correction voltage.