Testing Storage Parity Checking Logic
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-18
The parity checking logic of a random-access storage (RAM) is tested by forcing bad parity into a storage address, then reading out the same storage address yielding parity error. A typical RAM configuration is shown in the figure. The data portion 10 of the RAM is a standard chip of 2K by 8 bits. The other chip 11 is a standard 4K by 1 bit (M1 and M2). Either 2K half of chip 11 may be used as the parity bits for the data RAM 10. Ability to force bad parity into the RAM is provided by a bit in a hardware register 12 that controls a multiplexer 13 to switch either of the 2K by 1 bit segments in chip 11 to the data bus 14. In the embodiment, a microprocessor program controls the hardware register bit 12. The program initiates the following sequence in order to test the parity checking circuits: 1.