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Embedded Array Test Structure for AC Assurance

IP.com Disclosure Number: IPCOM000064420D
Original Publication Date: 1985-May-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Fields, DB Kazi, AM [+details]

Abstract

Array circuit performance measurements may be made by connecting the array to an external tester which provides stimuli and categorizes the responses. In the case of array macros, there are two significant limitations to this technique. The first is tester accuracy. Improvements to chip technology have resulted in arrays with very fast access times, and the present generation of testers may not accurately measure such fast access times. The second limitation is due to the additional input/output circuits that are necessary to connect the array macro to the chip pads. The delay of these additional circuits cannot be measured directly but must be obtained by either simulation or measurements on other circuits.