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Bit-Pushing Approach to VLSI Circuit Self-Testing

IP.com Disclosure Number: IPCOM000064422D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Barzilai, A Chandra, AK [+details]

Abstract

A scheme for self-testing vary-large-scale integrated (VLSI) circuits is presented in this disclosure. The self-testing method includes applying a large number of pseudo-random patterns to the circuits and generating a signature of the outputs. This requires the addition of one extra exclusive-OR circuit to each shift-register latch (SRL) to enable both input generation and signature accumulator. The invention minimizes hardware, and does not add significant delay to the circuit. The scheme is easy to automate, is largely transparent to the logic design process and to physical placement and wiring, and it can be applied to level-sensitive scan design (LSSD) or unmodified circuits. As shown in Fig. 1, which is a diagram of a complete LSSD system, the SRLs of the circuit are connected in one or more shift-register chains.