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Bit Line Voltage Test Circuit

IP.com Disclosure Number: IPCOM000064442D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Chan, YH Chin, WB Seeger, RO Struk, JR [+details]

Abstract

Due to low cell current attribute, bipolar arrays using complementary transistor switch (CTS) cells are sensitive to leakages and device degradation. In order to improve chip functionality and reliability, a test circuit is provided on chip to stress-test the memory cells. The test circuit will generate a pseudo forward bias condition on the outboard (bit) Schottky barrier diodes (SBDs) of the CTS cells in half- select state. This will stress the half-select cells (cells with selected word lines but unselected bit lines) for data retention problems caused by SBD forward voltage shift or leakages. Design Description In a CTS RAM (random-access memory), a cell is selected by lowering its word lines and raising its bit rail (Fig. 1).