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Cross-Coupled Front End Master-Slave Flip-Flop

IP.com Disclosure Number: IPCOM000064448D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Gray, KS [+details]

Abstract

A low capacitance master-slave flip-flop load on the bit lines of a display RAM shift register is featured. The use of a bootstrapped isolation scheme also gives the designer the flexibility to use either an 8.5-volt or 5.0-volt power supply. The use of a cross-coupled front end for a master-slave flip-flop enhances the signal strength and performance by adding a stage of amplification (transistors A1-A9) ahead of the flip-flop (Fig. 1). Transistors A1 and A2 are connected to the bit line to pass differentially sensed data to the cross-coupled amplifier. The front end design isolates the large capacitance of the master-slave flip-flop (transistors 1-12) from attenuating the data being sensed on the bit lines. Transistors A6 and A7 restore nodes BST and BSC to VDD.