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Metallized Ceramic Substrate With Low Inductance

IP.com Disclosure Number: IPCOM000064466D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-18

Publishing Venue

IBM

Related People

Authors:
Landrock, J Maier, H Perske, M Schmidt, M Tandjung, H [+details]

Abstract

To reduce the inductance of the electrical connection for the voltage supply of a semiconductor chip 1, the following steps are taken: Connector pins 2, connecting the conductors 5, 6, arranged on the surface 3 of a ceramic substrate 4 carrying semiconductor chip 1, to a multilayer printed circuit card 7, are soldered to surface 3. Multilayer printed circuit card 7 has plated through holes 8 into which connector pins 2 are soldered. Bottom side 9 of circuit card 7 is provided with a recess 10 for semiconductor chip 1. Recess 10 extends up to ground plane 11 which also serves to discharge the dissipation heat generated in chip 1.