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CMOS Inverter Optimization

IP.com Disclosure Number: IPCOM000064476D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Baier, E Haug, W Loehlein, W Mueller, R [+details]

Abstract

A concept is described for significantly reducing the rise or fall time of an output signal edge without increasing the other edge correspondingly. To that end, the P device of the inverter stage is replaced by a cascade circuit. Fig. 1 shows the usual CMOS inverter stage. For a symmetrical curve of its output signal, the width ratio of the P and the N transistor must be 3 : 1. This means that the input capacity of the inverter is primarily determined by the P transistor. The rise time of the positive or the fall time of the negative output signal edge may be reduced by increasing the size of the P or the N transistor. However, for keeping the input capacity constant, the respective other transistor has to be decreased in size, which immediately affects the other output signal edge. Fig.