Memory Error Correction Technique
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19
This article relates generally to digital memory correction and more particularly to a system of automatic substitution of a spare for a failing memory chip or its interface module. As the density of memory chips continues to increase, error detection and correction in small capacity data processing systems, such as a memory using 64K x 4 bit chips, become an unreasonable portion of the memory cost. Error correcting codes are expensive because of the large number of logic gates and redundant bits required to correct multi-bit errors in proportion to the memory capacity. Memory cost can be reduced by employing an inexpensive modified single-error-correct/double-error-detect (SEC/DED) code with a card design having one or more spare memory chips and VLSI interface modules.