Direct Memory Access Utilization Modulator
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19
During direct-memory access (DMA) transfers over a system bus, a microprocessor is halted and denied access to the bus. If DMA transfers are frequent, the microprocessor processing ability and system throughput can suffer. This processing device controls the percentage of system bus bandwidth used by DMA transfers. Thus, it can dynamically optimized system throughput. This bandwidth allocation is accomplished by using logic known as DMA utilization modulator. When the utilization modulator receives a DMA request, it counts a programmable number of bus cycles before presenting the request to the CPU. These bus cycles are therefore guaranteed to be available for CPU processing purposes. The CPU can thus use this device to create the optimum balance between DMA transfers and CPU processing to maximize system throughput.