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Test Generation for FET Switching Circuits

IP.com Disclosure Number: IPCOM000064482D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Beetem, JF Oklobdzija, VG Roth, JP [+details]

Abstract

As the complexity of VLSI circuits continues to increase, the need to test for failures has become imperative. The problem of generating test to detect failures on FET transistor networks has been unsolved for all but simple cases. In this article we describe an effective method for computing test for failures for FET switching networks. Here we define a function-preserving, failure-preserving transformation of a switching network, into a logic network. There are efficient means for computing tests for failures in logic networks, specifically, the D-algorithm. Tests so computed for the image logic network are automatically tests for failures in the original switching network. In other words the logic network so generated not only computes the same function; it also has the same failure-structure.