Browse Prior Art Database

Mated Array Chip Configuration

IP.com Disclosure Number: IPCOM000064486D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Rossi, F Straehle, W [+details]

Abstract

The proposed chip package allows doubling the bit density per unit area as well as providing functional unit configurations. Two identical semiconductor chips with common (interchangeable) input/output pads are - somewhat displaced - mated together by conventional C4 (controlled collapse chip connection) chip-joining technology. The I/O pads, located along the edge of the mating chips, are used for connection to chip carrier leads. Flip-chip solder joining, wire- and tape-bonding technologies are nowadays used in an exclusive way to connect the input/output pads of a single VLSI chip to substrate/carrier pins or leads. Chip-to-chip interconnection is effected on substrates or by other interconnection packaging technologies using cards or boards. With reference to the figures, it is proposed that two identical chips A, B (Fig.