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Parallel Testing of Several Chips of a Semiconductor Wafer

IP.com Disclosure Number: IPCOM000064499D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Hanna, R Loebling, H Mischke, K [+details]

Abstract

For testing several chips of a wafer in parallel, the chips must be non-defective, to ensure reliable test results. If that precondition is not met, falsified results are obtained, as the chips are interconnected through the silicon of the wafer and a short-circuit, mechanical damage or a process defect of a chip may affect the test results of the non-defective chips. To remedy this, the chips to be tested in parallel are, first of all, successively tested for defects, for instance, by measuring their leakage current. As defective chips must be precluded from parallel testing, each chip to be thus tested must have its own voltage supply. By disconnecting its voltage supply, a defective chip is isolated from non-defective ones which are subsequently tested in parallel.