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Sidewall Technology for Metal Step Coverage

IP.com Disclosure Number: IPCOM000064506D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Iyer, SS [+details]

Abstract

This article describes a method which minimizes the effects of poor step coverage, such as electromigration, high step resistance and the like. Metal coverage at steps is a serious performance and reliability concern in VLSI. At steps, the vertical surface on the chip is usually not completely covered by evaporated metal. The result is a local thinning of the metal cross section at the step. In addition, the material at the step is usually more porous. The result of these conditions is that the line resistance over the step increases and the step is a reliability hazard both from the point of view of electromigration and corrosion. Techniques to improve the step coverage include contouring the step gently, using more conformal methods of metal deposition such as sputtering and CVD.