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Electronic Mask Verification Disclosure Number: IPCOM000064508D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

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Davis, JW Folta, AC Portuondo, I [+details]


A technique is described whereby mask sets, used to manufacture very large-scale integrated (VLSI) circuit chips and memory chips are automatically checked for defects prior to the fabrication of the integrated circuit. The mask set is generated from a Graphics Language (GL/1) description which is stored in a computer data base. At this point in time, the GL/1 is known to be correct because it has been checked extensively by software programs that ensure its logical and physical accuracy. The mask fabrication process may introduce defects into the mask set. Prior art required the masks to be checked manually by visual comparison of a plot based on the GL/1 description of each mask level required in the fabrication process and a photographic enlargement of the corresponding mask.