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Single-Error Correction, Double-Error Detection Code Matrix for Microprocessors

IP.com Disclosure Number: IPCOM000064510D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Maule, WE [+details]

Abstract

A technique is described whereby microprocessor logic required for the implementation of a single-error correction, double-error detection code is reduced by the use of a new code matrix. Microprocessor instruction sets, such as in the IBM Series/1, include a number of byte operations that require memory to execute read and write cycles on an eight-bit byte rate. On a byte read cycle, the processor requires that both halves of the channel data bus contain the byte of data read from memory. Due to technology constraints on simultaneous switching of output drivers, one logic module cannot simultaneously output all sixteen data bus bits. To accommodate this restriction, two logic modules, blocks 10 and 11, as shown in Fig. 1, are used to drive the sixteen data bus lines.