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CMOS Dynamic Address Buffer Without the Use of a Reference Voltage

IP.com Disclosure Number: IPCOM000064512D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Hanafi, HI Lipa, R [+details]

Abstract

This article describes a circuit which eliminates the need of a reference voltage generator in the design of CMOS dynamic address buffers. The address buffer circuit is shown in Fig. 1. Transistors T2, T3, T4, T5 and T6 form the address latch. The input signal ADDX is fed to the gate of transistors T3 and T5 in the address latch through the transfer device T1. Transistor T1 gate is clocked by the signal CSIN. During standby, CSIN is kept high (VDD volts). This enables the input signal ADDX to control the state of the address latch. The output signals AX and AXN are held at a low state (0 volts) through transistors T9 and T10 which are clocked by the CSIN signal. When the memory is activated, CSIN goes low, as shown in Fig. 2, latching the ADDX signal statically into the address latch.