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IBM Series/1 Processor Operation Register Enhancement to Anticipate the Next Source Instruction Disclosure Number: IPCOM000064520D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

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Related People

Francis, E Kantner, R Thatcher, L Wyatt, V [+details]


A technique is described whereby the performance of the IBM Series/1 is increased through the use of hardware instead of utilizing firmware to decode the operation (OP) register. Special decodes are utilized to increase the instruction performance by anticipating the next instruction source. Within the IBM Series/1 OP register, many of the instructions use different fields to calculate a jump address, to obtain an effective address or to obtain an operand. In prior art, decoding of the fields was performed with microcode. In the enhanced version, the following method is used: At the beginning of the instruction execution phase, the OP register is put into the storage data register (SDR). The microinstruction can source special fields within the SDR.