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IBM Series/1 Performance Improvement Relative to Stop-On-Address Mode Disclosure Number: IPCOM000064530D
Original Publication Date: 1985-Jul-01
Included in the Prior Art Database: 2005-Feb-19

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Maule, WE Thatcher, LE Wyatt, VD [+details]


A technique is described whereby the IBM Series/1 microcode instructions are modified so as to provide a faster stop-on-address operation. This modification provides for faster overall performance during the execution of a stop-on-address branch instruction. The stop-on-address instruction is used as a debug tool in the IBM Series/1. From the program console, a logical address for the stop is entered. This logical address, an address key and a sixteen-bit logical address are entered into the relocation translator so as to generate a physical address. This physical address is then loaded into a stop- on-address physical register. When the processor is in the run state and the physical address to storage matches the stop-on-address physical register, the processor is put into a stop state with a stop-on- address comparison.