Browse Prior Art Database

Self-Aligned Recessed Gate MESFET

IP.com Disclosure Number: IPCOM000064548D
Original Publication Date: 1985-Aug-01
Included in the Prior Art Database: 2005-Feb-19

Publishing Venue

IBM

Related People

Authors:
Harder, CS Jaeckel, H Wolf, P [+details]

Abstract

A self-aligned MESFET device is fabricated by growing, on a semi-insulating substrate, first an epitaxial film that forms the FET channel and, on top of it, a highly doped layer serving as a connection to ohmic contacts subsequently applied. After deposition of an insulating film, a trench is etched in the gate region, down to the channel. Gate insulation is obtained using sidewall techniques. A cross-section of the basic structure is shown in the figure. On a Si GaAs substrate the n-channel of proper thickness and doping and the highly n-doped contact connection layer of GaAs are grown using MBE or MOCVD techniques. On top of this a non-alloyed ohmic contact, for instance, of the germanide type, is formed and the whole layer structure thereafter covered with an insulator, e.g., Si3N4 or SiO2 .